[Macchiato] DRAM/PCIe remapping

[Ard Biesheuvel]

On 9 August 2017 at 16:00, Matt Sealey <neko at bakuhatsu.net> wrote:
>
> Hi guys,
>
> Apologies for not replying to a current thread, I just subscribed..
>
> Further to the discussion on PCIe graphics cards and DRAM, I've been struggling here to
> get the board to recognize that I was a little cash-happy and got the 16GB package from
> SolidRun. I've spent a couple months being consummately disappointed in only being able
> to reference 4GB from UEFI and Linux.
>
> Ard's DRAM/PCIe remap patch seems to work relatively well
> but the existing code doesn't
> map enough memory in the MMIO32 space for me; if I have a card that has 2GB on it,
> I'd
> like to stuff it in the lower 32-bit space. Is it
> really necessary
> to put any DRAM at
> all in the lower 32-bit space apart from the code setting up the
> windowing being in
> that DRAM at the time? Could we dedicate
> the lower ~3GB or so
> to the PCIe space, and
> put a window of up to 16GB DRAM at a high physical
> address
> (what's the
> physical addressing
> limit on mochi?)
>
> I'm failing to find any reasonable documentation on the io remapping units, and things
> that might be in the way (the ATF diagrams seem to be Just Enough Information (tm) to
> get you into trouble without really explaining why) so my poking
> on this is limited to
> pulling apart patches and trying to figure out the intent..
>
> The other question is, is the limit of 4GB DRAM solely a device tree issue combined
> with this?
>
> # ARM Pcds
> gArmTokenSpaceGuid.PcdSystemMemoryBase|0
> gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000
> gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36
>
>
> Or am I missing something? Is that '36' evidence of an upper limit for windowing
> the DRAM up high? How does UEFI handle a sparse memory map if the 'base' is 0 and
> it has a size, but not a way of breaking this out?
>

Hi Matt,

First of all, using your 16 GB of DRAM is simply a matter of
redefining PcdSystemMemorySize to 0x4_0000_0000. The reason I did not
put that in is because mine was shipped with 4 GB, and we currently
have no means to detect it automatically.

For PCIe, it should be possible to change the remapping windows to
only map the first 1 GB of DRAM at 0x0, and put everything else at
0x1_0000_0000 and beyond. This should leave ample space for PCIe
MMIO32, although I wonder why you need all that space below 4 GB. Is
that a performance concern?