[Macchiato] PCIe access under u-boot for mcbin

[Marcin Wojtas]

Hi Frederik,

ARM-TF is ready to support extended PCIE windows @0xc0000000 and
@0x800000000. Maybe you are using some old version of it? Can you show the
bootlog from the very beginning?

Best regards,
Marcin

2018-04-24 17:34 GMT+02:00 Ard Biesheuvel <ard.biesheuvel at linaro.org>:

> On 24 April 2018 at 17:32, Frederik Lotter
> <frederik.lotter at netronome.com> wrote:
> > Hi,
> >
> > The uboot build for mcbin get PCIe range data from the included DT.
> >
> >  ranges =
> > <0x81000000 0 0xf9000000 0  0xf9000000 0 0x10000
> >   0x82000000 0 0xf6000000 0  0xf6000000 0 0xf00000>;
> >
> > Using uboot I can access BAR0 memory area inside uboot using a
> > standard Intel network card
> >
> > Marvell>> pci 1
> > Scanning PCI devices on bus 1
> > BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
> > _____________________________________________________________
> > 01.00.00   0x8086     0x1521     Network controller      0x00
> > 01.00.01   0x8086     0x1521     Network controller      0x00
> > Marvell>> pci bar 01.00.00
> > ID   Base                Size                Width  Type
> > ----------------------------------------------------------
> >  0   0x000000f6000000  0x00000000100000  32     MEM
> >
> > Marvell>> md.l 0x000000f6000000 10
> > f6000000: 081c0241 081c0241 80280780 00000000    A...A.....(.....
> > f6000010: 0008471e 00000026 001400c0 0000004e    .G..&.......N...
> > f6000020: 1411000a 00000000 00c28001 00000100    ................
> > f6000030: 00008808 00000000 81008100 00000000    ................
> >
> > However, for our network card we need a much bigger BAR size, so
> > out DT entry is (which I took from the Linux DT which works):
> >
> > ranges =
> > <0x81000000 0 0xf9000000 0  0xf9000000 0 0x10000
> >   0x82000000 0 0xc0000000 0  0xc0000000 0 0x20000000>;
> >
> > Scanning PCI devices on bus 1
> > BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
> > _____________________________________________________________
> > 01.00.00   0x8086     0x1521     Network controller      0x00
> > 01.00.01   0x8086     0x1521     Network controller      0x00
> > Marvell>> pci bar 01.00.00
> > ID   Base                Size                Width  Type
> > ----------------------------------------------------------
> >  0   0x000000c0000000  0x00000000100000  32     MEM
> >
> > md.l ---> Abort
> >
> > However I get a data abort.
> >
> > Is this likely just a memory map setup problem in u-boot, or does this
> > larger BAR size require additional SMMU or other setup not done in
> u-boot?
> >
> > The memory map document for Armada 8040 specify the PCIe range from
> > 0xf6000000 so my first guess is I need to modify the page table mapping?
> >
>
> Hello Frederik,
>
> There are several levels of physical address remapping in the 8040 SoC
> that all need to point to the PCIe controller. These settings are done
> in ARM Trusted Firmware IIRC, and I had to modify them to make a
> memory window of sufficient size (256 MB config space and 512 MB MMIO
> space) available for PCIe.
>
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