[Macchiato] PCIe access under u-boot for mcbin
Frederik Lotter
frederik.lotter at netronome.com
Wed Apr 25 08:02:49 BST 2018
On Tue, Apr 24, 2018 at 6:07 PM, Marcin Wojtas <mw at semihalf.com> wrote:
> Hi Frederik,
>
> ARM-TF is ready to support extended PCIE windows @0xc0000000 and
> @0x800000000. Maybe you are using some old version of it? Can you show the
> bootlog from the very beginning?
>
BootROM - 2.03
Starting CP-0 IOROM 1.07
Booting from SD 0 (0x29)
Found valid image at boot postion 0x002
lNOTICE: Starting binary extension
NOTICE: SVC: SW Revision 0x0. SVC is not supported
mv_ddr: mv_ddr-armada-17.10.4-gcc280f0 (Apr 25 2018 - 06:57:16)
mv_ddr: completed successfully
NOTICE: Cold boot
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v1.3(release):armada-17.10.7:4396548
NOTICE: BL1: Built : 06:57:31, Apr 25 2018
NOTICE: BL1: Booting BL2
lNOTICE: BL2: v1.3(release):armada-17.10.7:4396548
NOTICE: BL2: Built : 06:57:34, Apr 25 2018
BL2: Initiating SCP_BL2 transfer to SCP
NOTICE: SCP_BL2 contains 2 concatenated images
NOTICE: Load image to CP1 MSS
NOTICE: Loading MSS image from address 0x4023020 Size 0x1378 to MSS at
0xf4280000
NOTICE: Done
NOTICE: Load image to AP MSS
NOTICE: Loading MSS image from address 0x4024398 Size 0x1f68 to MSS at
0xf0580000
N
FreeRTOS 7.3.0 - Marvell cm3 - A8K release armada-17.10.1
OTICE: Done
NOTICE: SCP Image doesn't contain PM firmware
NOTICE: BL1: Booting BL31
lNOTICE: MSS PM is not supported in this build
NOTICE: BL31: v1.3(release):armada-17.10.7:4396548
NOTICE: BL31: Built : 06:57:41, Apr 25 2018
l
U-Boot 2017.03-armada-17.10.2-g6a6581a-dirty (Apr 25 2018 - 06:56:38 +0000)
Model: MACCHIATOBin-8040
Clock: CPU 2000 [MHz]
DDR 1200 [MHz]
FABRIC 1200 [MHz]
MSS 200 [MHz]
DRAM: 4 GiB
U-Boot DT blob at : 000000007f70ec38
EEPROM configuration pattern not detected.
Comphy chip #0:
Comphy-0: PEX0
Comphy-1: PEX0
Comphy-2: PEX0
Comphy-3: PEX0
Comphy-4: SFI
Comphy-5: SATA1
Comphy chip #1:
Comphy-0: SGMII1 1.25 Gbps
Comphy-1: SATA0
Comphy-2: USB3_HOST0
Comphy-3: SATA1
Comphy-4: SFI
Comphy-5: SGMII2 3.125 Gbps
UTMI PHY 0 initialized to USB Host0
SATA link 0 timeout.
SATA link 1 timeout.
AHCI 0001.0000 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
flags: 64bit ncq led only pmp fbss pio slum part sxs
SATA link 0 timeout.
going to start mss_periodic_ihb_wa for mss
SATA link 1 timeout.
AHCI 0001.0000 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
flags: 64bit ncq led only pmp fbss pio slum part sxs
pci_uclass_pre_probe, bus=0/pcie at f2600000, parent=cp110-master
decode_regions: len=14, cells_per_record=7
decode_regions: region 0, pci_addr=f9000000, addr=f9000000, size=10000,
space_code=1
- type=1, pos=0
decode_regions: region 1, pci_addr=c0000000, addr=c0000000, size=20000000,
space_code=2
- type=0, pos=1
PCIE-0: Link up (Gen2-x4, Bus0)
pci_uclass_post_probe: probing bus 0
pci_bind_bus_devices: bus 0/pcie at f2600000: found device 0, function 0
pci_find_and_bind_driver: Searching for driver: vendor=11ab, device=110
pci_find_and_bind_driver: No match found: bound generic driver instead
pci_auto_config_devices: start
PCI Autoconfig: Bus Memory region: [c0000000-dfffffff],
Physical Memory [c0000000-dfffffffx]
PCI Autoconfig: Bus I/O region: [f9000000-f900ffff],
Physical Memory [f9000000-f900ffffx]
pci_auto_config_devices: device pci_0:0.0
PCI Autoconfig: Found P2P bridge, device 0
PCI Autoconfig: BAR 0, I/O, size=0xfff4, address=0xf9000000
bus_lower=0xf900fff4
dm_pci_hose_probe_bus
pci_get_bus_max: ret=0
dm_pci_hose_probe_bus: bus = 1/pci_0:0.0
pci_uclass_pre_probe, bus=1/pci_0:0.0, parent=pcie at f2600000
pci_uclass_post_probe: probing bus 1
pci_bind_bus_devices: bus 1/pci_0:0.0: found device 0, function 0
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=1521
pci_find_and_bind_driver: No match found: bound generic driver instead
pci_bind_bus_devices: bus 1/pci_0:0.0: found device 0, function 1
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=1521
pci_find_and_bind_driver: No match found: bound generic driver instead
pci_auto_config_devices: start
pci_auto_config_devices: device pci_1:0.0
PCI Autoconfig: BAR 0, Mem, size=0x100000, address=0xc0000000
bus_lower=0xc0100000
PCI Autoconfig: BAR 1, I/O, size=0x20, No room in resource
PCI Autoconfig: BAR 2, Mem, size=0x4000, address=0xc0100000
bus_lower=0xc0104000
PCI Autoconfig: ROM, size=0x80000, address=0xc0180000 bus_lower=0xc0200000
pci_auto_config_devices: device pci_1:0.1
PCI Autoconfig: BAR 0, Mem, size=0x100000, address=0xc0200000
bus_lower=0xc0300000
PCI Autoconfig: BAR 1, I/O, size=0x20, No room in resource
PCI Autoconfig: BAR 2, Mem, size=0x4000, address=0xc0300000
bus_lower=0xc0304000
PCI Autoconfig: ROM, size=0x80000, address=0xc0380000 bus_lower=0xc0400000
pci_auto_config_devices: done
pci_get_bus_max: ret=1
pci_auto_config_devices: done
MMC: sdhci at 6e0000: 0, sdhci at 780000: 1
Net: eth0: mvpp2-0 [PRIME]mdio_register: non unique device name
'ethernet at 0'
, eth1: mvpp2-3, eth2: mvpp2-4, eth3: mvpp2-5
Hit any key to stop autoboot: 0
Marvell>>
Marvell>>
Marvell>> pci 1
Scanning PCI devices on bus 1
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
01.00.00 0x8086 0x1521 Network controller 0x00
01.00.01 0x8086 0x1521 Network controller 0x00
Marvell>> pci bar 01.00.00
ID Base Size Width Type
----------------------------------------------------------
0 0x000000c0000000 0x00000000100000 32 MEM
Marvell>>
Marvell>> md.l 0x000000c0000000 10
c0000000:"Synchronous Abort" handler, esr 0x96000006
ELR: 7ff7da08
LR: 7ff7d9e0
x0 : 0000000000000009 x1 : 0000000000000000
x2 : 000000000000003a x3 : 00000000c0000000
x4 : 0000000000000000 x5 : 000000007ff9cbbe
x6 : 0000000000000004 x7 : 000000000000000f
x8 : 000000007f70e750 x9 : 0000000000000008
x10: 000000007f70e3b9 x11: 0000000000000021
x12: 0000000000000008 x13: 00000000ffffffff
x14: 000000007f70eb0c x15: 000000007f70ec38
x16: 000000007ff9b11b x17: 000000007ff971a6
x18: 000000007f715d18 x19: 0000000000000010
x20: 00000000c0000000 x21: 00000000c0000000
x22: 0000000000000004 x23: 0000000000000008
x24: 0000000000000009 x25: 0000000000000004
x26: 0000000000000004 x27: 000000007f70e918
x28: 0000000000000000 x29: 000000007f70e890
Resetting CPU ...
resetting ...
>
> Best regards,
> Marcin
>
> 2018-04-24 17:34 GMT+02:00 Ard Biesheuvel <ard.biesheuvel at linaro.org>:
>
>> On 24 April 2018 at 17:32, Frederik Lotter
>> <frederik.lotter at netronome.com> wrote:
>> > Hi,
>> >
>> > The uboot build for mcbin get PCIe range data from the included DT.
>> >
>> > ranges =
>> > <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
>> > 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
>> >
>> > Using uboot I can access BAR0 memory area inside uboot using a
>> > standard Intel network card
>> >
>> > Marvell>> pci 1
>> > Scanning PCI devices on bus 1
>> > BusDevFun VendorId DeviceId Device Class Sub-Class
>> > _____________________________________________________________
>> > 01.00.00 0x8086 0x1521 Network controller 0x00
>> > 01.00.01 0x8086 0x1521 Network controller 0x00
>> > Marvell>> pci bar 01.00.00
>> > ID Base Size Width Type
>> > ----------------------------------------------------------
>> > 0 0x000000f6000000 0x00000000100000 32 MEM
>> >
>> > Marvell>> md.l 0x000000f6000000 10
>> > f6000000: 081c0241 081c0241 80280780 00000000 A...A.....(.....
>> > f6000010: 0008471e 00000026 001400c0 0000004e .G..&.......N...
>> > f6000020: 1411000a 00000000 00c28001 00000100 ................
>> > f6000030: 00008808 00000000 81008100 00000000 ................
>> >
>> > However, for our network card we need a much bigger BAR size, so
>> > out DT entry is (which I took from the Linux DT which works):
>> >
>> > ranges =
>> > <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
>> > 0x82000000 0 0xc0000000 0 0xc0000000 0 0x20000000>;
>> >
>> > Scanning PCI devices on bus 1
>> > BusDevFun VendorId DeviceId Device Class Sub-Class
>> > _____________________________________________________________
>> > 01.00.00 0x8086 0x1521 Network controller 0x00
>> > 01.00.01 0x8086 0x1521 Network controller 0x00
>> > Marvell>> pci bar 01.00.00
>> > ID Base Size Width Type
>> > ----------------------------------------------------------
>> > 0 0x000000c0000000 0x00000000100000 32 MEM
>> >
>> > md.l ---> Abort
>> >
>> > However I get a data abort.
>> >
>> > Is this likely just a memory map setup problem in u-boot, or does this
>> > larger BAR size require additional SMMU or other setup not done in
>> u-boot?
>> >
>> > The memory map document for Armada 8040 specify the PCIe range from
>> > 0xf6000000 so my first guess is I need to modify the page table mapping?
>> >
>>
>> Hello Frederik,
>>
>> There are several levels of physical address remapping in the 8040 SoC
>> that all need to point to the PCIe controller. These settings are done
>> in ARM Trusted Firmware IIRC, and I had to modify them to make a
>> memory window of sufficient size (256 MB config space and 512 MB MMIO
>> space) available for PCIe.
>>
>> _______________________________________________
>> Macchiato mailing list
>> Macchiato at lists.einval.com
>> https://lists.einval.com/cgi-bin/mailman/listinfo/macchiato
>
>
>
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